1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device having a device separation area of burying type, and more particularly to a method for manufacturing a semiconductor device in which a groove formed on a substrate and a resist pattern are positioned by self-alignment to be useful to make an integrated circuit fine.
2. Description of the Related Art
In accordance with fining the integrated circuit, the separation distance between the devices has been made smaller every generation. A device ,separation area of burying type has been used.
A conventional device separation area of burying type and its manufacturing method will be explained with reference to FIGS. 1 to 5.
FIGS. 1 to 5 are cross sectional views showing the conventional device separation area of burying type shown by every main process.
First, as shown in FIG. 1, a silicon oxide film (SiO.sub.2) 102 having a thickness of about 100 nm is formed on a silicon (Si) substrate 100 by thermal oxidization. Then, a mask (not shown), formed of photoresist, is formed by photographic etching. By use of such a mask, a groove 104 is formed on the substrate 100 of the device separation forming section by RIE.
Sequentially, a silicon oxide film (SiO.sub.2) 106 having a thickness of about 500 nm is formed on the upper entire surface of the substrate 100, and is buried in the groove 4.
As shown in FIG. 2, the silicon oxide film 106 formed on the upper entire surface of the substrate 100 is etched back by RIE, so that a device separation area 108 can be obtained.
The device separation area 108 should be logically formed as shown in FIG. 2. However, in actual, as shown in FIG. 3, the edge of the separation area 108 is caved along a side wall of the groove 104. The side wall portion of the groove 104 is a boundary between different materials of silicon and a silicon oxide film. Due to this, stress concentrates in such an area. Etching in the area where stress concentrates advances faster than an area where stress does not concentrate. Due to this, the edge of the separation area 108 is caved along the side wall of the groove 104.
Moreover, if the substrate 100 is repeatedly etched by the formation of a gate oxidization or isotropic etching during the manufacture, the edge of the separation area 108 may be largely caved along the side wall of the groove 104. If the caved portion is formed, pressure to a diffusion layer 110 to be formed later is lowered, and this may cause increase in reverse leak current. Moreover, in a case where gate electrode covers the caved portion, a threshold voltage is locally reduced by concentration of an electrical field to the substrate corner from the gate electrode, and gate insulation pressure is reduced.
Moreover, as shown in FIG. 5, if a polycrystalline silicon 112 is left on the cave portion of the edge of the separation area to form the gate electrode using polycrystalline silicon to be a predetermined shape by anisotropic etching, short-circuit defective may be caused between the gate electrodes through the residual polycrystalline silicon 112.
The above-mentioned prior art is described in U.S. Pat. No. 4,160,991, Jpn. Pat. Applin. KOKAI publication No. 59-50541, and Jpn. Pat. Applin. KOKAI publication No. 60-97661.
In order to prevent the disadvantage caused when the cave portion is formed, an insulation material is buried in the groove, and the upper portion of the groove is capped with the other insulation material. Then, the insulation materials are processed by use of the resist pattern by photographic etching. As a result, the insulation materials cover the semiconductor substrate over a fixed range of the surroundings of the groove, thereby preventing the cave portion from being formed.
In processing the insulation materials, a difference in level is easily generated between the insulation materials and the semiconductor substrate. In the post-processes, the difference level may cause a wiring process defective such as short-circuit between the electrodes due to the rest of etching.
In order to prevent such a problem, it has been known that an inclination is formed on the side surface of the insulation material to smoothly connect the wire to the semiconductor substrate.
Such a technique is disclosed in e.g., Jpn. Pat. Applin. KOKAI publication No. 2-304926, Jpn. Pat. Applin. KOKAI publication No. 3-16152 and Jpn. Pat. Applin. KOKAI publication No. 1-107554.
However, in the technique disclosed in the above documents, the size of the area of the resist pattern must be larger than the width of the groove in consideration of positioning the resist pattern and the groove. This fails to satisfy the requirement of making the integrated circuit fine. Moreover, the inclination can be formed on the side surface of the insulation material by isotropic etching in which impurity ion is implanted into the surface of the insulation material and speed increasing etching is provided. However, in consideration of over-etching, an area, which is larger than the surface area of the semiconductor substrate to be covered, is required in the resist pattern. Due to this, since the minimum distance, which is the boundary between the peripheral pattern and the device itself, becomes larger than a desirable minimum distance, the fine processing is interrupted.